cr1901

@echo off
rem Autogenerated by Migen

yosys -q -l top.rpt top.ys || exit /b
arachne-pnr  -d 1k -P tq144 -p top.pcf top.blif -o top.txt || exit /b
icetime  -P tq144 -d hx1k -c 0.0 -t -p top.pcf -r top.tim top.txt || exit /b
icepack  top.txt top.bin || exit /b

cr1901

CAPI=1
[main]
description = YM2151-compatible core

[fileset src_files]
files =
 jt51/jt51.v
 jt51/jt51_acc.v
 jt51/jt51_envelope.v
 jt51/jt51_exp2lin.v

cr1901

#!/usr/bin/env python3

from migen import *
from migen.build.platforms import icestick

class Rot(Module):
    def __init__(self):
        self.clk_freq = 12000000
        self.ready = Signal()
        self.rot = Signal(4)

cr1901

my_hello1: my_hello1.smt2
	yosys-smtbmc -s z3 --dump-smt2 my_hello1_full_bmc.smt2 --dump-vcd my_hello1_bmc.vcd my_hello1.smt2
	yosys-smtbmc -s z3 -i --dump-smt2 my_hello1_full_tmp.smt2 --dump-vcd my_hello1_tmp.vcd my_hello1.smt2

my_hello1.smt2: my_hello1.v
	yosys -ql my_hello1.yslog \
		-p 'read_verilog -formal my_hello1.v' \
		-p 'prep -top my_hello -nordff' \
		-p 'clk2fflogic; opt_clean' \
		-p 'write_verilog my_hello_clk2ff.v' \

cr1901

#![no_std]
#![feature(const_fn)]
#![feature(asm)]

use core::cell::UnsafeCell;


pub struct MspAtomicBool {
    data: UnsafeCell<u8>,
}

cr1901

CFG_ENABLE_DEBUG     := 1
CFG_ENABLE_LLVM_LINK_SHARED := 1
CFG_LOCALSTATEDIR    := /var/lib
CFG_SYSCONFDIR       := /etc
CFG_DATADIR          := /share
CFG_INFODIR          := /share/info
CFG_LLVM_ROOT        := /home/william/Projects/build-llvm-lm32
CFG_PYTHON           :=
CFG_JEMALLOC_ROOT    :=
CFG_BUILD            :=

cr1901

# SPI flash has been zeroed out deliberately in the "free area" at this point.
# New firmware has been loaded using MimasV2Config.py.
# First Memory Dump: Read SPI flash contents before writing.
# Second Memory Dump: Read SPI flash contents after writing (0xFF => 0x00).

H2U 00:01:39>
H2U 00:01:39>debug spiflash
Free space begins at 200BB134, size 332723 bytes.
Memory dump:
0x200bb134  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................

cr1901

William@William-THINK MINGW32 ~/src/radare2-regressions
$ make
git pull https://github.com/radare/radare2-regressions.git
From https://github.com/radare/radare2-regressions
 * branch            HEAD       -> FETCH_HEAD
Already up-to-date.
radare2 1.3.0-git 11992 @ windows-x86-32 git.0.10.4-147-g95283d5
commit: 95283d5531aefa7160e720ec7af86d4a6dec8249 build: 2016-08-03
[BR]  1  0000:
[XX]  1  archs: endian tests: mips

cr1901

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 22.267ns (Maximum Frequency: 44.909MHz)
   Minimum input arrival time before clock: 2.083ns
   Maximum output required time after clock: 5.996ns
   Maximum combinational path delay: 1.328ns

Timing Details:

cr1901

#include <generated/csr.h>
#include <generated/mem.h>
#include <irq.h>

#include "ym2151.h"

extern volatile unsigned int num_samples;

int main(int argc, char * argv[])
{