hanetzer

$ cargo run --bin amd prox570.4402.bin
    Finished dev [unoptimized + debuginfo] target(s) in 0.00s
     Running `target/debug/amd prox570.4402.bin`
EFS {
    magic: 0x55AA55AA,
    rsvd_04: 0x0,
    rsvd_08: 0x0,
    rsvd_0c: 0x0,
    psp_legacy: 0x0,
    psp: 0x130000,

hanetzer

$ binwalk T3500A02.0.rom

DECIMAL       HEXADECIMAL     DESCRIPTION
--------------------------------------------------------------------------------
65544         0x10008         Microsoft executable, portable (PE)
2015309       0x1EC04D        Copyright string: "Copyright 2008 JETWAY SECURITY MICRO.INC   Build on 2008-05-04"
2077238       0x1FB236        mcrypt 2.2 encrypted data, algorithm: blowfish-448, mode: CBC, keymode: 8bit
2096292       0x1FFCA4        mcrypt 2.2 encrypted data, algorithm: blowfish-448, mode: CBC, keymode: 8bit
2096944       0x1FFF30        Copyright string: "Copyright 1985-1988 Phoenix Technologies Ltd. Copyright 1988-2009 Dell Inc.   All rights reserved."
2096992       0x1FFF60        Copyright string: "Copyright 1988-2009 Dell Inc.   All rights reserved."

hanetzer

Namespace(file='u-boot-hi3516dv300_emmc.reg', svd='hi3516dv300.svd', offset=0, size=0)
reg        value      delay      attrs
0x12010080 0x00000000 0x00000000 0x000000fd WRITE CRG:PERI_CRG32[31:0] (SoC clock selection register)
                                                  field sysapb_cksel[11:10] (SYSAPB clock select)
                                                  field syscfg_cksel[9:8] (SYSCFG clock select)
                                                  field sysaxi_cksel[8:6] (SYSAXI clock select)
                                                  field ddr_cksel[6:3] (DDR SDRAM clock select)
                                                  field a7_cksel[3:0] (A7 clock select)
0x120101e0 0x00000000 0x00000000 0x00550000  READ CRG:PERI_CRG120[10:0] (SoC frequency indicator register)
                                                  field fmc_sc_seled[15:12] (FMC clock switch completion indicator)

hanetzer

$ python hisireg.py --file u-boot-hi3516dv300_emmc.reg --svd hi3516dv300.svd --size 0 && hexdump -C u-boot-hi3516dv300_emmc.reg
Namespace(file='u-boot-hi3516dv300_emmc.reg', svd='hi3516dv300.svd', offset=0, size=0)
reg        value      delay      attrs
0x12010080 0x00000000 0x00000000 0x000000fd WRITE CRG:PERI_CRG32[31:0] (SoC clock selection register)
0x120101e0 0x00000000 0x00000000 0x00550000  READ CRG:PERI_CRG120[10:0] (SoC frequency indicator register)
0x00000000 0x00000000 0x00000064 0x00000000 DELAY 100
0x12010010 0x12d55555 0x00000000 0x000000fd WRITE CRG:CRG_PLL4[31:0] (EPLL configuration register 0)
0x12010014 0x0000102d 0x00000000 0x000000fd WRITE CRG:CRG_PLL5[31:0] (EPLL configuration register 1)
0x00000000 0x00000000 0x00000064 0x00000000 DELAY 100
0x120101e8 0x0000000f 0x00000000 0x001d0000  READ CRG:PERI_CRG_PLL122[3:0] (PLL lock status register)

hanetzer

#!/usr/bin/env python3

import argparse
from colorama import Fore, Style
from cmsis_svd.parser import SVDParser
import struct
import sys

SPC = "                                                  "

hanetzer

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2017-2022 Marty Plummer <[email protected]>
 */

#include "hi3521a.dtsi"

/ {
	model = "RaySharp RS-DM-290E DVR Board";
	compatible = "raysharp,rs-dm-290e", "hisilicon,hi3521a";

hanetzer

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2017-2022 Marty Plummer <[email protected]>
 */

#include <dt-bindings/clock/hi3521a-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
	#address-cells = <1>;

hanetzer

hi3521a_crg_rd: PERI_CRG13 offset 0x0034 val 0x07001605
hi3521a_crg_rd: PERI_CRG29 offset 0x0074 val 0x00000000
hi3521a_crg_rd: PERI_CRG33 offset 0x0084 val 0x00000000
hi3521a_crg_rd: PERI_CRG30 offset 0x0078 val 0x00000000
hi3521a_crg_rd: PERI_CRG33 offset 0x0084 val 0x00000000
hi3521a_sysctrl_rd: offset 0x0000 val 0x00000212
hi3521a_crg_rd: PERI_CRG33 offset 0x0084 val 0x00000000
hi3521a_crg_wr: PERI_CRG33 offset 0x0084 val 0x00008000
hi3521a_crg_rd: PERI_CRG33 offset 0x0084 val 0x00008000
hi3521a_crg_wr: PERI_CRG33 offset 0x0084 val 0x00000000

hanetzer

hisilicon # tftp 0x82000000 uImage.hi3535;tftp 0x84000000 rootfs.cpio.uboot;bootm 0x82000000 0x84000000
MAC:   00-00-23-34-45-66
TFTP from server 192.168.99.91; our IP address is 192.168.99.76
Download Filename 'uImage.hi3535'.
Download to address: 0x82000000
Downloading: #################################################
done
Bytes transferred = 4336640 (422c00 hex)
MAC:   00-00-23-34-45-66
TFTP from server 192.168.99.91; our IP address is 192.168.99.76

hanetzer

// SPDX-License-Identifier: GPL-2.0-or-later
#include <dt-bindings/clock/hi3535-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;