Skip to content

Instantly share code, notes, and snippets.

View josyb's full-sized avatar

Josy Boelen josyb

  • Citium CommV
  • Elewijt, Belgium
  • 00:34 (UTC +01:00)
View GitHub Profile
@josyb
josyb / ListOfConstants.py
Created March 15, 2015 19:08
List of Constants in MyHDL
'''
Created on 14 Mar 2015
@author: Josy
'''
from __future__ import print_function
import os, random
from myhdl import *
@josyb
josyb / geschema.py
Created March 26, 2015 13:56
Guy Eschemann: TypeError: Unexpected type
from myhdl import *
def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
# table = tuple([9,8,7,6])
@always_seq(clk.posedge, reset=rst)
def fsm_seq():
for i in range(4):
# s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = table[i]
@josyb
josyb / myhdl_issue43_jb
Created April 25, 2015 18:20
reworked and reformatted example from MyHDL issue#43
from __future__ import print_function
import random
from myhdl import *
def m_top_const(COEF, N, clock, reset, a, b, x, y):
v = [Signal(x.val) for _ in range(N-1)]
@josyb
josyb / simpletristateexample.py
Last active August 29, 2015 14:22
a simple tristate pin example in MyHDL
'''
Created on 18 May 2015
@author: Josy
'''
from __future__ import print_function
from myhdl import *
'''
Created on 27 Mar 2015
@author: Josy
'''
import os
from myhdl import *
@josyb
josyb / aos.vhd
Last active August 31, 2015 14:09
MyHDL Structured Types in action.
-- File: aos.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Aug 31 15:57:52 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
@josyb
josyb / test_xx.py
Created September 8, 2015 19:10
A MyHDL test_ template for Eclipse
'''
Created on ${date}
@author: ${user}
'''
from __future__ import print_function
# optional import to mark 'xfail' tests
import py.test
@josyb
josyb / test_array_part_3.py
Last active September 14, 2015 14:05
Issue with having to ad a 'delta'after clk,posedge
def array_3(clk, reset, Sel1, Sel2, Q):
''' testing a 2-dimensional Constant Array
'''
aoc = myhdl.Array( [[1,2,3], [4,5,6], [7,8,9]], myhdl.intbv(0)[len(Q):])
@myhdl.always_seq( clk.posedge, reset = reset)
def rtlreg():
Q.next = aoc[Sel2][Sel1]
return rtlreg
def array_2(clk, reset, D, Q):
''' testing a 2-dimensional Array
just making a simple pipeline
'''
mt = myhdl.Array( (4, 3,), myhdl.Signal( myhdl.intbv(0)[len(D):]))
@myhdl.always_comb
def rtlcomb():
Q.next = mt[3][2]
@josyb
josyb / another_test.py
Last active September 19, 2015 08:04
another small test to demonstrate the 'delta' issue
def delta(Clk, Reset, D, Wr, Sel, Q):
r = [Signal( intbv(0)[len(D):]) for _ in range(9)]
@always_seq(Clk.posedge, reset = Reset)
def rtl():
if Wr:
r[0].next = D
r[1].next = r[0]
r[2].next = r[1]
r[3].next = r[2]