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/* Syscalls for AARCH64 :
 *   - registers are 64-bit
 *   - stack is 16-byte aligned
 *   - syscall number is passed in x8
 *   - arguments are in x0, x1, x2, x3, x4, x5
 *   - the system call is performed by calling svc 0
 *   - syscall return comes in x0.
 *   - the arguments are cast to long and assigned into the target registers
 *     which are then simply passed as registers to the asm code, so that we
 *     don't have to experience issues with register constraints.

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# Build a static executable this way :
$ gcc -fno-asynchronous-unwind-tables -fno-ident -s -Os -nostdlib \
            -static -include nolibc.h -lgcc -o hello hello.c

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#!/bin/bash

# verilog
sudo apt -y install iverilog gtkwave yosys yosys-doc

# netlistsvg
curl -fsSL https://deb.nodesource.com/setup_current.x | sudo -E bash -
sudo apt -y install nodejs
sudo npm install -g netlistsvg

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module fulladder #(
    parameter width = 2
) (
    input [width:0] a,
    input [width:0] b,
    input c_in,
    output c_out,
    output [width:0] sum
);

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module fulladder_tb;
    localparam width = 2;
    // 1. Declare testbench variables
    reg [width:0] a;
    reg [width:0] b;
    reg c_in;
    wire [width:0] sum;
    integer i;

    // 2. Instantiate the design and connect to testbench variables

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NAME := fulladder
SRC := $(NAME).v
TB := $(NAME)_tb.v
VCD := $(NAME)_tb.vcd
OUT := $(NAME).o
JSON := $(NAME).json
SVG := $(NAME).svg

target:
	iverilog -o $(OUT) $(SRC) $(TB) || exit 1

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iverilog -o fulladder.o fulladder.v fulladder_tb.v || exit 1
vvp fulladder.o
a=0x0 b=0x0 c_in=0x0 c_out=0x0 sum=0x0
a=0x4 b=0x1 c_in=0x1 c_out=0x0 sum=0x6
a=0x3 b=0x5 c_in=0x1 c_out=0x1 sum=0x1
a=0x5 b=0x2 c_in=0x1 c_out=0x1 sum=0x0
a=0x5 b=0x6 c_in=0x1 c_out=0x1 sum=0x4

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module counter # (
    parameter width = 4
) (
        input   clk,
        input   rstn,
        output  reg [width - 1:0]       out
);
    always @ (posedge clk) begin
        if (!rstn) begin
            out <= out + 1;

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## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc
## This file is a general .xdc for the Arty A7-100 Rev. D
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];

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## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc
## This file is a general .xdc for the Arty A7-100 Rev. D
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];