cr1901’s gists

cr1901 / sim_cd.py

Last active August 29, 2015 14:26

Migen Simulation with manually-specified clock domain

	from migen.fhdl.std import *
	from migen.sim.generic import run_simulation, Simulator, TopLevel
	from migen.sim.icarus import Runner

	# Suppose this is the module I'm interested in seeing the output of:
	class CounterWithReset(Module):
	def __init__(self):
	self.counter = Signal(32)
	self.reset = Signal(1)
	self.clock_domains.slow = ClockDomain()

cr1901 / get_csrs.py

Last active August 26, 2015 19:44

Migen BankArray

	class YMScope(Module, AutoCSR):
	def __init__(self, cpu_core, device_to_test):
	self.submodules.stop_cpu = CSRStorage(8)
	# Will not actually generate a bank... BankArray doesn't actually
	# check whether the object passed in has a get_csrs method.
	# BankArray only checks whether the object's attributes have a get_csr
	# method. Why is that?
	# MiSoC's SoC class inherits from AutoCSR, but calling csrgen.BankArray succeeds- BankArray
	# detects the SoC's get_csrs function. What am I doing wrong?
	self.submodules.csrbankarray = csrgen.BankArray(self, mem_map, data_width=8, address_width=16)

cr1901 / bracket.js

Last active September 10, 2015 01:25

Three.js Solvespace Export HTML Test

	/* Autogenerated Three.js viewer for Solvespace Model (copy into another document):
	<!DOCTYPE html>
	<html lang="en">
	<head>
	<meta charset="utf-8"></meta>
	<title>Three.js Solvespace Mesh</title>
	<script src="http://threejs.org/build/three.min.js"></script>
	<script src="http://threejs.org/examples/js/controls/OrthographicTrackballControls.js"></script>
	<script src="final_mesh.js"></script>
	</head>

cr1901 / mesh.html

Created September 5, 2015 04:58

solvespace.js Prototypee

	<!DOCTYPE html>
	<html lang="en">
	<head>
	<meta charset="utf-8"></meta>
	<title>Three.js Solvespace Mesh</title>
	<script src="http://threejs.org/build/three.min.js"></script>
	<script src="http://threejs.org/examples/js/controls/OrthographicTrackballControls.js"></script>
	<script src="mesh.js"></script>
	<script src="solvespace.js"></script>
	</head>

cr1901 / case.py

Created September 16, 2015 12:08

Migen Case Bug?

	from migen import *
	from migen.fhdl import verilog

	class CaseTest(Module):
	def __init__(self):
	self.a = Signal(1)
	self.b = Signal(1)
	self.choose = Signal(1)
	self.o = Signal(1)

cr1901 / cat.py

Created September 17, 2015 13:03

Migen Cat With inouts Generates Invalid Verilog

	from migen import *
	from migen.fhdl import verilog

	class CatTest(Module):
	def __init__(self):
	self.a = Signal(1)
	self.b = Signal(1)
	self.c = Cat([self.a, self.b])
	self.d = Signal(2)

cr1901 / led2.py

Created September 18, 2015 10:10

Migen Current vs New Compare

	new=True

	if new:
	from migen import *
	from migen.build.platforms import mercury
	bn="led2_new"
	else:
	from migen.fhdl.std import *
	from mibuild.platforms import mercury
	bn="led2"

cr1901 / test_results.txt

Created September 20, 2015 07:57

Migen Test Results 87a85319

	$ python3 -m unittest
	.........................................E
	======================================================================
	ERROR: test_asic_syntax (test_syntax.SyntaxCase)
	----------------------------------------------------------------------
	Traceback (most recent call last):
	File "F:/Projects/migen/migen/test\test_syntax.py", line 62, in test_asic_syntax
	self.base_test("asic", True, options)
	File "F:/Projects/migen/migen/test\test_syntax.py", line 45, in base_test
	stderr=subprocess.DEVNULL, shell=True)

cr1901 / baudgen.py

Last active September 21, 2015 00:54

Clock Divider with Minimal Resource Usage

	from migen import *
	from migen.fhdl import verilog

	class BaudGen(Module):
	def __init__(self):
	self.divider = Signal(16)
	self.half_period_cnt = Signal(16)
	self.next_cnt = Signal(16)
	self.out = Signal(1)

cr1901 / recur.py

Created September 22, 2015 12:29

Migen Simulator "Recursion Depth Exceeded" Example

	from migen import *

	class Recur(Module):
	def __init__(self):
	self.divider = Signal(16)
	self.half_of_divider = Signal(16)

	###

	self.sync += [self.half_of_divider[:15].eq(self.divider[1:] - 1)]

William D. Jones cr1901