mithro

<?xml version="1.0"?>
<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
  <models>
    <model name="dsp_combinational">
      <input_ports>
        <port combinational_sink_ports="out" name="a"/>
        <port combinational_sink_ports="out" name="b"/>
        <port combinational_sink_ports="out" name="m"/>
      </input_ports>

mithro

Valid

<models>
  <xi:include href="../common_slice/common_slice.model.xml" xpointer="xpointer(models/child::node())" />
  <model name="blah">
  </model>
</models>

mithro

{
  "creator": "Yosys 0.8+319 (git sha1 2c7e2541, x86_64-conda_cos6-linux-gnu-gcc 1.23.0.449-a04d0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/tmp/really-really-really-really-really-really-really-really-really-really-really-really-really-long-path/conda/conda-bld/yosys_1555106055240/work=/usr/local/src/conda/yosys-0.8 -fdebug-prefix-map=/github/SymbiFlow/symbiflow-arch-defs/build/env/conda=/usr/local/src/conda-prefix -fPIC -Os)",
  "modules": {
    "A5FFMUX": {
      "attributes": {
        "CLASS": "routing",
        "blackbox": 1,
        "src": "../common_slice/routing/N5ffmux/a5ffmux.sim.v:9"
      },
      "ports": {

mithro

----------------------- minitests/roi_harness/README.md -----------------------
index 35d4111..6d57316 100644
@@ -1,35 +1,124 @@
 # ROI_HARNESS Minitest
 
 ## Purpose
 
-Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness
+Creates an harness bitstream which maps peripherals into a region of interest
+which can be reconfigured.

mithro

Register	ABI Name	Description	Saver
x0	zero	Hard-wired zero	—
x1	ra	Return address	Caller
x2	sp	Stack pointer	Callee
x3	gp	Global pointer	—
x4	tp	Thread pointer	—
x5–7	t0–2	Temporaries	Caller
x8	s0/fp	Saved register/frame pointer	Callee
x9	s1	Saved register	Callee

mithro

from migen import *


class M(Module):
  def __init__(self):
    self.i_data = Signal()
    self.o_data = Signal()
    self.sync += [
      self.o_data.eq(self.i_data),

mithro

Info: Critical path report for clock 'usb_48_clk_$glb_clk' (posedge -> posedge): 
Info: curr total                                                              
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$14086_DFFLC.O   
Info:  5.0  6.4    Net usb_rx_o_ep[2] budget 0.852000 ns (15,27) -> (15,12)      
Info:                Sink $abc$46676$auto$blifparse.cc:492:parse_blif$47207_LC.I0
Info:  1.3  7.7  Source $abc$46676$auto$blifparse.cc:492:parse_blif$47207_LC.O
Info:  1.8  9.4    Net $abc$46676$n4103_1 budget 0.852000 ns (15,12) -> (15,11)  
Info:                Sink $abc$46676$auto$blifparse.cc:492:parse_blif$47206_LC.I1
Info:  1.2 10.7  Source $abc$46676$auto$blifparse.cc:492:parse_blif$47206_LC.O 

mithro

***************************************************************************
WARNING: the following submodules do not match expected commit:

+ea895e01466431bd75c1b7f8f74f3f0dd54b6a09 third_party/valentyusb (heads/master)

If you are not developing in submodules you may need to run:

git submodule update --init --recursive

mithro

Memory Regions

• ROM - rom
• SRAM - sram
• User FLASH - user_flash
• Main RAM - main_ram

ROM

• Generally blockram inside the FPGA with the write enable disabled.

mithro

module top(
	input clk16,
	output reg spiflash_cs_n,
	output reg spiflash_clk,
	output reg spiflash_mosi,
	input spiflash_miso,
	output spiflash_wp,
	output spiflash_hold,