mkatsimpris

from myhdl import *



def mul(ina,inb,out1,clk,reset,width=8):

  ina_reg,inb_reg=[intbv(0,-2**width,2**(width-1)) for i in range(2)]
  out_reg=intbv(0,-2**(2*width),2**(2*width-1))
  @always_seq(clk.posedge, reset=reset)
  def logic():

mkatsimpris

 
  constant C_Y_1       : signed(14 downto 0) := to_signed(4899,  15);
  constant C_Y_2       : signed(14 downto 0) := to_signed(9617,  15);
  constant C_Y_3       : signed(14 downto 0) := to_signed(1868,  15);
  constant C_Cb_1      : signed(14 downto 0) := to_signed(-2764, 15);
  constant C_Cb_2      : signed(14 downto 0) := to_signed(-5428, 15);
  constant C_Cb_3      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_1      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_2      : signed(14 downto 0) := to_signed(-6860, 15);
  constant C_Cr_3      : signed(14 downto 0) := to_signed(-1332, 15);

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from math import *
from ram import *

class buf_fifo_int_in(object):

mkatsimpris

#!/usr/bin/env python
# coding=utf-8

from myhdl import *

@block
def RAM(dout, din, raddr,waddr, we, clk,addr_width=8, data_width=24):

    """  Ram model """
    mem = [Signal(intbv(0)[data_width:]) for i in range(int(2**addr_width))]

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from math import *
from ram import *
from myhdl.conversion import *

class buf_fifo_int_in(object):

mkatsimpris

#!/bin/python
from myhdl import *

ACTIVE_LOW, INACTIVE_HIGH = False, True
INACTIVE_LOW, ACTIVE_HIGH = False, True


def sintbv(value, nbits):
    nbits -= 1
    min_value = -1 << nbits

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from myhdl.conversion import *
from random import randrange

const = [-2, -3]

mkatsimpris

1)N=bits pou prepei na athroisw kai input to shma mou
2) exw ena component enan adder me inputs:a,b kai output:c=====> adder(a,b,c)
3) exw array apo signals gia na ta exw ekei gia na ginei swsta to port map. kanw assign ekei ta outputs ton adders. 
este oti to leme out array. epishs to megethos tou einai N-1 kai exei ta outputs twn endiameswn adders. esy tha oriseis to bitwidth.
gia n>4
for i in 0 to log2(N) - 2:
  for j in 0 to N/2 - 2*i - 1:
      if i==0 generate:
          adder(input(2*j),input(2*j+1),out(j))
      else generate:

mkatsimpris

@myhdl.block
def dct_2d(inputs, outputs, clock, reset, num_fractional_bits=14):

    first_1d_output = output_interface()

    first_1d = dct_1d(inputs, first_1d_output, clock,
                      reset, num_fractional_bits)

    inputs_2nd_stage = [input_1d_2nd_stage(first_1d_output.out_precision)
                        for _ in range(8)]

mkatsimpris

#!/usr/bin/env python
# coding=utf-8

import numpy as np
from math import sqrt, pi, cos
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_comb, always_seq, ConcatSignal
from myhdl.conversion import analyze
from jpegenc.subblocks.common import (input_interface,
                                      output_interface)