tanakamura

module top
   (
    input CLK100MHZ,
    input [3:0] btn,
    output [3:0] led
    );

   reg [31:0] counter;

   always @(posedge CLK100MHZ)

tanakamura

set projName l_ug

proc cp { } {                   # creat proj
    global projName
    create_project $projName $projName -part xc7a35ticsg324-1L -force
}

proc op { } {                   # open proj
    global projName
    open_project $projName/$projName.xpr

tanakamura

#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>

int main(int argc, char **argv)
{
    int n = 0;
    char buf[1024];

    if (argc >= 2) {

tanakamura

#include <unistd.h>
#include <stdio.h>
#include <time.h>

double sec(void) {
    struct timespec tv;

    clock_gettime(CLOCK_MONOTONIC, &tv);

    return tv.tv_sec + tv.tv_nsec / (1000000000.0);

tanakamura

#include <unistd.h>
#include <time.h>
#include <stdio.h>

double sec(void) {
    struct timespec tv;

    clock_gettime(CLOCK_MONOTONIC, &tv);

    return tv.tv_sec + tv.tv_nsec / (1000000000.0);

tanakamura

#include <windows.h>
#include <stdio.h>

int main() {
    int nloop = 1024, i;
    LARGE_INTEGER freq, t0, t1;

    QueryPerformanceFrequency(&freq);

    QueryPerformanceCounter(&t0);

tanakamura

#include <stdio.h>

int main() {

}

tanakamura

module top(
           input clk_12M,
           output LED1,
           output LED2,
           output LED3,
           output LED4,
           output LED5,
           output LED6,
           output LED7,
           output LED8,

tanakamura

all: top.bin

top.blif: top.v
	yosys -p "synth_ice40 -blif top.blif; clean ; write_verilog synth.v" top.v

top.txt: top.blif top.pcf
	arachne-pnr -p top.pcf top.blif -o top.txt -d 8k -P ct256

top.bin: top.txt
	icepack top.txt top.bin

tanakamura

#include <immintrin.h>
#include <x86intrin.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>

static inline
__m256i mm256_u8gather_epu8(const uint8_t* lut, __m256i vindex, __m256i andMask) {

    __m256i lo = _mm256_unpacklo_epi8(vindex, _mm256_setzero_si256());