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Henry Gomersall hgomersall

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@hgomersall
hgomersall / jinja.py
Last active December 25, 2015 04:19
A SCons tool for building Jinja files
import SCons.Builder
import SCons.Tool
from SCons.Errors import StopError
import jinja2
from jinja2 import FileSystemLoader
from jinja2.utils import open_if_exists
from jinja2.exceptions import TemplateNotFound
import os
@hgomersall
hgomersall / trivial_multiple_instantiation.py
Last active August 29, 2015 14:15
A trivial case showing multiple created processes from an identical source.
from myhdl import *
def TrivialTest(sig_out, sig_in, reset, clock):
@always_seq(clock.posedge, reset=reset)
def _trivial_test():
sig_out.next = sig_in
return _trivial_test
@hgomersall
hgomersall / interface_twiddler.py
Last active August 29, 2015 14:17
Interface int conversion
from myhdl import *
def interface_twiddler(interface, clock, reset):
@always_seq(clock.posedge, reset=reset)
def twiddle():
interface.a.next = interface.b + interface.c
return twiddle
@hgomersall
hgomersall / vga_fifo.py
Created April 3, 2015 08:16
A modified functional version of code in http://permalink.gmane.org/gmane.comp.python.myhdl/4091
from myhdl import *
CACHE_SIZE = 20
NUM_OF_ADDRESSES = 25
# entity creation:
def vga_fifo(
# ports:
clk,
rst,
@hgomersall
hgomersall / output_assignment.vhd
Created April 3, 2015 11:21
An example VHDL file showing a clock being written, with an assignment inbetween.
-- File: /tmp/tmpsSOg4v/dut_convertible_top.vhd
-- Generated by MyHDL 0.9dev
-- Date: Fri Apr 3 10:04:52 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
@hgomersall
hgomersall / two_clocks.py
Created April 7, 2015 16:31
from myhdl import *
from multiprocessing import Process, current_process, Value, Event, Semaphore
process_count = Value('i', 0)
sync_semaphore = Semaphore()
all_synced = Event()
def synchronise():
with sync_semaphore:
process_count.value += 1
@hgomersall
hgomersall / confused_sim.py
Last active August 29, 2015 14:20
An example myhdl sim showing an earlier sim stepping on the toes of a later one.
from myhdl import *
PERIOD = 10
A = Signal(intbv(0)[25:])
clock = Signal(bool(0))
reset = ResetSignal(0, async=False, active=1)
def ClockSource(clock):
@hgomersall
hgomersall / multiple_sims.py
Last active August 29, 2015 14:20
myhdl working multiple sim instances
from myhdl import *
a = Signal(intbv(0)[5:])
clock = Signal(False)
reset = ResetSignal(False, active=True, async=False)
def clockgen(clock):
@instance
def clkgen():
@hgomersall
hgomersall / myhdl_multithreaded_sims.py
Last active August 29, 2015 14:20
An example myhdl sim showing two sims running concurrently in different threads with no problem. In such an example, it is necessary to have separate signals, otherwise they *will* step on each other.
from myhdl import *
import threading
a = Signal(intbv(0)[5:])
b = Signal(intbv(0)[5:])
clock1 = Signal(False)
clock2 = Signal(False)
reset1 = ResetSignal(False, active=True, async=False)
@hgomersall
hgomersall / no_converted_unsign_with_concat.py
Created May 27, 2015 11:09
Concat converts to VHDL with no explicit unsign
from myhdl import *
def twiddler(sig_in, sig_out, clock, reset):
concat_sig_in = ConcatSignal(sig_in(5, 0), intbv(0)[5:])
@always_seq(clock.posedge, reset=reset)
def twiddle():
sig_out.next = concat_sig_in.signed()