Skip to content

Instantly share code, notes, and snippets.

View cfelton's full-sized avatar

Christopher Felton cfelton

View GitHub Profile
import myhdl
from myhdl import Signal
from myhdl import intbv
from myhdl import instance
from myhdl import always
def example_instance(clock, rx_bit_cnt, restart, tomax=111):
from __future__ import division
from __future__ import print_function
from myhdl import *
"""
This module contains two designs that implement bank permutations. The
bank permutator takes an array input and maps to a differently ordered
array output.
@cfelton
cfelton / name_conflicts.py
Created July 7, 2015 13:51
MyHDL toVHDL name conflicts (reported by others) works with vcom fails with GHDL.
from random import randint
from myhdl import *
def pipe(xi, xo, clock, reset, N=8):
buffer = [Signal(xi.val) for _ in range(N)]
@always_seq(clock.posedge, reset=reset)
def rtl():
from __future__ import print_function
from __future__ import division
import os
from random import randint
from math import log
from pprint import pprint
from collections import OrderedDict
import pickle
@cfelton
cfelton / spi_master_model.py
Last active August 29, 2015 14:23
rapid modeling - break the ice
from __future__ import division
from __future__ import print_function
from myhdl import *
from zintf import IBus
from zintf import SPIBus
from spi_slave import SPISlave
def vhdl_stub(sigi, sigo):
vhdl_stub.id = vhdl_stub.id + 1
this_id = vhdl_stub.id
@always_comb
def assign():
sigo.next = not sigi
return assign
vhdl_stub.vhdl_code ="""
foo_bar_$this_id: entity work.blah(myhdl)
"""
from random import randint
from myhdl import *
# output from the following tristate example
# Driver1 Driver2 Tristate
# None None None
# None 1 1
# 0 None 0
# None 1 1
@cfelton
cfelton / test_interfaces4.py
Last active September 2, 2015 13:28
test that demonstrates the interface conversion error in the myhdl tip
from myhdl import *
"""
This set of tests exercies a peculiar scenario where an
expanded interface is Signal is flagged as having multiple
drivers. This appears to be a name collision in the name
expansion and was introduced in ....
"""
class Intf1(object):
@cfelton
cfelton / ADXL345.py
Last active August 29, 2015 14:20
simple ADXL345 model (3-wire SPI only)
from __future__ import division
from __future__ import print_function
from random import randint
from myhdl import *
class ADXL345(object):
@cfelton
cfelton / sigmat.py
Last active February 14, 2018 01:10
Signal Matrix implemented in myhdl
from myhdl import *
class SignalMatrix(object):
def __init__(self, size=(4,4,), stype=intbv(0)[9:]):
# the size of the matrix
self.size = size
nrows, ncols = size