cr1901

Using CC=i686-w64-mingw32-gcc
Using CXX=i686-w64-mingw32-gcc
Using LD=i686-w64-mingw32-gcc
Compiling with CUDD
Using pthreads
Found GCC_VERSION 5.3.0
Found GCC_MAJOR>=4
Using CFLAGS=-Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -x c++ -fpermissive -w -DABC_USE_CUDD=1 -DABC_USE_PTHREADS
`` Generating dependency: /src/bdd/llb/llb4Sweep.c
./depends.sh i686-w64-mingw32-gcc `dirname src/bdd/llb/llb4Sweep.c` -g -O -Isrc -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -x c++ -fpermissive -w -DABC_USE_CUDD=1 -DABC_USE_PTHREADS src/bdd/llb/llb4Sweep.c > src/bdd/llb/llb4Sweep.d

cr1901

module top(
    clk,
    sin,
    bit0,
    bit1,
    bit2,
    bit3,
    bit4,
    bit5,
    bit6,

cr1901

module top(
    clk,
    sin,
    bit0,
    bit1,
    bit2,
    bit3,
    bit4,
    bit5,
    bit6,

cr1901

root@arm:~# cat /var/log/Xorg.0.log
[  3697.150]
X.Org X Server 1.16.4
Release Date: 2014-12-20
[  3697.151] X Protocol Version 11, Revision 0
[  3697.151] Build Operating System: Linux 3.16.0-0.bpo.4-armmp-lpae armv7l Debian
[  3697.151] Current Operating System: Linux arm 4.4.1-armv7-x5 #1 SMP Mon Feb 1 09:43:37 UTC 2016 armv7l
[  3697.151] Kernel command line: console=ttyO2,115200n8 root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait coherent_pool=1M quiet
[  3697.151] Build Date: 11 February 2015  01:18:06AM
[  3697.152] xorg-server 2:1.16.4-1 (http://www.debian.org/support)

cr1901

[artiq] William@WILLIAM-THINK F:\Consult\artiq\artiq\artiq\test
> python -m unittest test_ctlmgr.py
fatal: --dirty is incompatible with commit-ishes
Controller lda_sim did not exit on request, ending the process
E
======================================================================
ERROR: test_start_ping_stop_controller (test_ctlmgr.ControllerCase)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "F:\Consult\artiq\artiq\artiq\test\test_ctlmgr.py", line 73, in test_start_ping_stop_controller

cr1901

/* Machine-generated using Migen */
module top(
	output gpio,
	output user_led,
	input clk12
);

wire __main___pll_outg;
wire __main___lock;
wire sys_clk;

cr1901

#include <limits.h>

/* Assume: short is 16-bits
twos-complement. */

short wrap(unsigned short a);

short wrap(unsigned short in)
{
  if(in < SHRT_MAX)

cr1901

#!/usr/bin/env python3

import argparse
from fractions import Fraction

from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.build.platforms import minispartan6
from migen.build.generic_platform import *

cr1901

/* Machine-generated using Migen */
module top(
	output user_led,
	output user_led_1,
	output user_led_2,
	output user_led_3,
	output user_led_4,
	input clk12
);

cr1901

Florent/MiSoC SPI Master

• Inherits from AutoCSR class to generate an API for writing to device.
• Control signals to connect to other hardware also CSR-bus compatible.
• Single-device master (only one CS_N signal)
• Configurable polarity, except data read/writes must be opposite polarity.
• Registers:
  • Status: Transfer is done/not done.
  • Length: Can set a number of bits to send. This number can exceed the bus width.
  • MISO: R/O Data input.
• MOSI: R/W Data output.